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TC93P27F
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC93P27F
DTS Microcontroller (DTS-21)
The TC93P27F is a 4-bit CMOS microcontroller for single-chip digital tuning systems, featuring a built-in 230-MHz prescaler, PLL, and LCD drivers. The CPU has 4-bit parallel addition and subtraction instructions (e.g., AI, SI), logic operation instructions (e.g., OR, AN), composite decision and comparison instructions (e.g., TM, SL), and time-base functions. The package is an 80-pin, 0.5 mm-pitch compact package. In addition to various input/output ports and a dedicated key-input port, which are controlled by powerful input/output instructions (IN1 to 3, OUT1 to 3), there are many dedicated LCD pins, a PWM output port, a BUZR port, a 6-bit A/D converter, a serial Weight: 0.45 g (typ.) interface, and an IF counter, etc. Low-voltage and low-current consumption make this microcontroller suitable for portable DTS equipment. TC93P27F has built-in One Time PROM that is able to be programmed by EPROM writer. TC93P27F is the same pin assignment as TC9327AF, therefore the program is written into the internal PROM of TC93P27F, and this IC operates as the same function as TC9327AF.
Features
* * * * * * * * * * * * * * * * * * * * * 4-bit microcontroller for single-chip digital tuning systems. Operating voltage VDD = 1.8 to 3.6 V, with low current consumption due to CMOS circuitry (with only the CPU operating when VDD = 3 V, IDD = 130 A max) Built-in prescaler (1/2 fixed divider +2 modulus prescaler: fmax 230 MHz) Features built-in 1/4-duty, 1/2-bias LCD drivers and a built-in 3 V booster circuit for the display. Data memory (RAM) and ports are easily backed up. Program memory (ROM): 16 bit x 7168 steps Data memory (RAM): 4 bit x 256 words 62-instruction set (all one-word instructions) Instruction execution time: 40 s (with 75-kHz crystal) (MVGS, DAL instructions: 80 s) Many addition and subtraction instructions (12 types each addition and subtraction) Powerful composite decision instructions (TMTR, TMFR, TMT, TMF, TMTN, TMFN) Data can be transmitted between addresses on the same row. Register indirect transfer available (MVGD, MVGS instructions). 16 powerful general registers (located in RAM) Stack levels: 2 Free branching (JUMP instructions) is allowed in the 7168 steps of program memory (ROM) as there are no pages or fields. 16 bits of any address in the 1024 program memory steps (ROM) can be referenced (DAL instructions). Features independent frequency input pins (FMIN and AMIN) and two (DO1 and DO2) phase comparator outputs for FM/VHF and AM. Seven kinds of reference frequencies can be selected via software. Powerful input/output instructions (IN1 to 3, OUT1 to 3). Dedicated input ports (K0 to K3) for key input, 29 LCD drive pins (100 segments maximum) available.
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* 29 I/O ports: 27 input/output programmable in 1-bit units, 1 output-only port, and 1 input-only port. The 2 IFIN, and DO1 pins can be switched by instruction to IN1 (input-only) or OT2 (output-only). In addition, 9 output LCD output pins for S17 to S25 can be switched to I/O port in 1-bit units. Three backup modes available by instruction: only CPU operation, crystal oscillation only, clock stop. Features a built-in 2-Hz timer F/F and a built-in 10/100 Hz interval pulse outputs (internal port for time base). Allows PLL lock status detection. Four of the LCD segment outputs (S22 to S25) can also operate as key return timing outputs (KR0 to KR3). The I/O ports are not dedicated for key return timing outputs but can have other uses as well. Built-in 20-bit, general-purpose IF counters can detect stations during auto-tuning by counting the intermediate frequencies of each band. Built-in buzzer output circuit can output 8 kinds of frequencies in 4 modes: continuous output, single-shot output, 10-Hz intermittent output, and 10-Hz intermittent 1-Hz interval output. Features built-in 12-bit PWM circuit usable for easy-to-use D/A converter. Features a built-in 3-channel, 6-bit A/D converter. To prevent CPU malfunction, a built-in supply voltage drop detection circuit shuts down the CPU when the voltage falls below 1.55 V. MASK ROM product: TC9327AF
* * * * * * * * * *
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TC93P27F
Pin-Assignment
Serial interface
Counter input
P2-3 (DC-REF)
P6-2 (CTRIN1)
P2-2 (ADIN3)
A/D converter P2-1 (ADIN2) P2-0 (ADIN1) P3-0 (SI)
P3-3 (BUZR)
P4-0 (PWM)
BUZR output P3-2 (SCK)
PWM output
P6-0
P5-3
P5-2
P5-1
P5-0
P4-3
P4-2
P6-1
P4-1
P3-1 (SO)
60 P6-3 (CTRIN2) MUTE TEST IFIN (IN1/SCIN) Phase comparator output Radio power DO1/OT2 DO2
HOLD
41 I/O port 40 P1-2 P1-1 P1-0 K3
61
PLL
P1-3
KEY input
K2 K1 K0
OT1 GND Local oscillator signal Battery FMIN AMIN VDD
RESET /VPP 75 kHz XOUT
Output port SVFP-80 Pin (0.5 mm pitch)
Input port
IN2 P9-3
I/O port
P9-2 Key return timing output P9-1 S25 (P9-0/KR0) S24 (P8-3/KR1) S23 (P8-2/KR2) S22 (P8-1/KR3) S21 (P8-0) S20 (P7-3) S19 (P7-2) S18 (P7-1)
PLL
XIN VXT VLCD C1 C2 VEE 80 1 COM1 COM2 COM3 COM4 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 LCD driver (4 25 = 100 segments max) 20 S16 21
S17 (P7-0)
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TC93P27F
Block Diagram
100 Hz
HOLD
500 Hz STOP X'tal OSC CPU timing gene. Reference divider 1 kHz 10 Hz 2 Hz F/F MPX/la. 7 PLL OFF 4 bit swallow counter/la. LF 1 kHz La. 20 bit IF counter Data bus P6-3/CTRIN2 La. Code bus P4-0/ PWM COLUMN Addr. Dec RAM (4 256 word) La. 12 bit PWM 8 bit BUZR P6-2/CTRIN1 REF Phase Com. SIG OT La. MUTE LOCK Detector DO1/OT2 DO2
XOUT XIN VXT
FM FMIN AMIN IFIN/IN1/ SCIN OT1 La. 1/2 VHF HF
PSC
1/15, 16
13 bit programmable counter/la.
Mute cont. I/O-1
4 C 4 B
Data Reg. (16 bit)
2 A One time PROM (16 7168 step) 4 G-reg
ROW P3-3/BUZR 4 R/W buf 4 4 SIO 8 bit shift Reg 4 La. P3-2/ SCK P3-1/SO P3-0/SI
3 VPP Addr. Dec. 4 Ca. 13 6 Prog. Counter 13 Judge 4 IC 6 Instruction Dec. ALU
La.
P2-3/DC-REF P2-2/ADIN3 La. P2-1/ADIN2 P2-0/ADIN1 6 bit A/D
13
Stack Reg. (2 level) VPP STOP Reset VEE 3 bit A/D Key la. Key Dec. La STOP F/F 1.5 V Const Volt. VEE
RESET /VPP
LCD/IO Cont./La. LCD 500 Hz COM VLCD VEE VLCD
Power on Reset Doubler Circuit
VDD GND
Segment driver/la.
La
Key Cont.
La.
La.
K0
K1
K2
COM1
COM4
IN2
S1
S2
S3
K3
C2
P9-1
P9-2
P9-3
P1-0
P1-1
P1-2
S17/P7-0
S21/P8-0
S22/P8-1/KR3
S25/P9-0/KR0
P1-3
C1
4
VLCD
VEE
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TC93P27F
Description of Pin Function
Pin No. 1 2 3 4 Symbol COM1 COM2 LCD common output COM3 COM4 Pin Name Function and Operation Output common signals to LCD panels. Through a matrix with pins S1 to S25, a maximum 100 segments can be displayed. Three levels, VLCD, VEE, and GND, are output at 62.5 Hz every 2 ms. VEE is output after system reset and CLOCK STOP are released, and a common signal is output after the DISP OFF bit is set to "0". Remarks
VLCD VEE
VLCD 5~20 S1 to S16 LCD segment output Segment signal output terminals for LCD panel. Together with COM1 to COM4, a matrix is formed that can display a maximum of 100 segments. S17/P7-0 21~25 S21/P8-0 S22/P8-1 /KR3 26~29 S25/P9-0/ KR0 LCD segment output/I/O port S17 to S25 are usable as I/O port by program. Signals for key matrix and the segment signals from pins S22/KR3 to S25/KR0 are output on a time sharing basis. 4 4 = 16 key matrix can be created in conjunction with key inport ports K0 to K3. LCD segment output/I/O port/key return timing output
Input instructio n
VLCD
30~32
P9-1~P9-3
I/O port 9
3-bit I/O port, capable of input/output setup for each bit via software.
Input instructio n
33
IN2
Input port 2
1-bit input port
Input instructio n
4-bit input port for key matrix input, capable of inputting a maximum of 4 4 = 16 key data in combination with the key return timing outputs (KR0 to KR3) of an LCD segment pin. Comprises an A/D comparator making it possible to RIN1 select high impedance with pull-down and pull-up pins for inputs, and to perform programming with a 3-bit input threshold. This allows various key RIN1 matrices to be formed. Also usable as a 4-channel 3-bit A/D converter with a successive comparison formula via software. When an "H" level is applied in key input ports set to pull-down mode, WAIT mode is canceled. Comparator
34~37
K0~K3
Key input port
Reference voltage
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Pin No. Symbol Pin Name Function and Operation The input and output of these 4-bit I/O ports can be programmed in 1-bit units. This pin is capable of outputting timing signals for the key matrix by program. 38~41 P1-0~P1-3 I/O port 1 It contains load resistance in N-ch, and can form the matrix for a push-key needing no diode for the key matrix. By altering the input of I/O ports set to input, the CLOCK STOP mode or the WAIT mode can be released, and the MUTE bit of the MUTE pin can be set to "1". 4-bit I/O ports, allowing input and output to be programmed in 1-bit units. P2-0/ADIN1 I/O port 2 /AD analog voltage input /AD analog voltage input /AD analog voltage input /Reference voltage input Pins P2-0 to P2-2 can also be used for analog input to the built-in 6-bit, 3-channel A/D converter. The conversion time of the built-in A/D converter using the successive comparison method is 280 ms. The necessary pin can be programmed to AD analog input in 1-bit units, and P2-3 can be set to the reference voltage input. Internal power supply (VDD) or constant voltage (VEE) can be used as the reference voltage. So battery voltage, etc., can be easily detected. The reference voltage input, for which a built-in operational amp. is used, has high impedance. The A/D converter and all associated controls are performed via software. 4-bit I/O ports, allowing input and output to be programmed in 1-bit units. Pins P3-0 to P3-2 can also be used for the I/O terminals of serial interface circuits (SIO). SIO functions for 4-bit or 8-bit serial data inputs from the SI pin and outputs from the SO pin at the SCK pin clock edge. The clock for serial operation ( SCK ) is capable of internal/external options and rise/fall shift options. The SO pin is also capable of switching to serial inputs (SI), facilitating the control of various LSI's and communication between controllers. All SIO inputs use built-in Schmitt circuits. P3-3 pins also functions as the output for a built-in buzzer. The buzzer output can select 8 kinds of 0.625 to 3 kHz frequencies with 4 modes: continuous output, single-shot output, 10-Hz intermittent output, and 10-Hz intermittent 1-Hz interval output. SIO, buzzer, and all associated controls can be programmed. SIO ON (excluding P3-3 pins)
Input instruction
Remarks
RON
P2-1/ADIN2 42~45 P2-2/ADIN3 P2-3/ DC-REF
To A/D converter
Input instruction
I/O port 3 P3-0/SI 46~49 P3-1/SO P3-2/ SCK P3-3/BUZR /Serial data input /Serial data output /Serial clock I/O /Buzzer output
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Pin No. Symbol Pin Name Function and Operation Remarks
16-bit I/O ports, allowing input and output to be programmed in 1-bit units. The P4-0 pin is also used for built-in 12-bit PWM outputs. The PWM outputs pulse continuously at 73.26 Hz, and can change the duty of the pulses to 256 steps (8 bits), causing the added pulses to be output using 4 bits for 16 cycles (218.5 ms). The P6-2 and P6-3 pins are also used for input purposes when using 20-bit IF counters as 12-bit and 8-bit binary counters. The P6-2 pin can be used for 12-bit binary counter inputs, and the P6-3 pin for 8-bit binary counter inputs. PWM outputs, counter inputs, and all associated controls can be programmed.
Input instruction
P4-0/ PWM P4-1 50~61 P6-2/CTRIN1 P6-3/CTRIN2
I/O port 4 /PWM output I/O port 4
(P4-0 to P6-1)
I/O port 6 /Counter input
(P6-2, P6-3)
1-bit output port, normally used for muting control signal output. 62 MUTE Muting output port This pin can set the internal MUTE bit to "1" according to a change in the input of I/O port 1. MUTE bit output logic can be changed: PLL phase difference can also be output using this pin.
Input pin used for controlling TEST mode. 63 TEST Test mode control input "H" (high) level indicates TEST mode, while "L" (low) indicates normal operation. The pin is normally used at low level or in NC (no connection) state. (a pull-down resistor is builtin). IF signal input pin for the IF counter to count the IF signals of the FM and AM bands and to detect the automatic stop position. The input frequency is between 0.35 to 12 MHz (0.2 Vp-p min). A built-in input amp. and C coupling allow operation at low-level input. The IF counter is a 20 bit counter with optional gate times of 1, 4, 16 and 64 ms. 20 bits of data can be readily stored in memory. This counter is used as a timer when the IF counter is not used. The input pin can be programmed for use as an input port (IN port). CMOS input is used when the pin is set as an IN port. Note: To set SCIN, use the pin with DC coupling and rectangular wave input. RfIN2 RIN2
64
IFIN/IN1/ SCIN
IF signal input /Input port /Cycle measurement input
PLL phase comparator output pins. When the prescaler output of the programmable counter is higher than the reference frequency, output is at high level. When output is lower than the reference frequency, output is at low level. When output equals the reference frequency, high impedance output is obtained. Because DO1 and DO2 are output in parallel, optional filter constants can be designed for the FM/VHF and AM bands. Pin DO1 can be programmed to high impedance or programmed as an output port (OT2). Thus, the pins can be used to improve lock-up time or used as output ports.
65
DO1/OT2
Phase comparator output /Output port Phase comparator output
66
DO2
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TC93P27F
Pin No. Symbol Pin Name Function and Operation Input pin for request/release hold mode. Normally, this pin is used to input radio mode selection signals or battery detection signals. Hold mode includes CLOCK STOP mode (stops crystal oscillation) and WAIT mode (halts CPU). Setting is implemented with the CKSTP instruction or the WAIT instruction. When the CKSTP instruction is executed, request/release of the hold mode depends on the internal MODE bit. If the MODE bit is "0" (MODE-0), executing the CKSTP instruction while the HOLD pin is at low level stops the generator and the CPU and changes to memory back-up mode. If the MODE bit is "1" (MODE-1), executing the CKSTP instruction enters memory back-up mode regardless of the level of the HOLD pin. Memory back-up is released when the HOLD pin goes high in MODE-0, or when the HOLD pin input changes in MODE-1. When memory back-up mode is entered by executing a WAIT instruction, any change in the HOLD pin input releases the mode. In memory back-up mode, current consumption is low (below 10 mA), and all the output pins (e.g., display output, output ports) are automatically set to low level. Remarks
67
HOLD
Hold mode control input
1-bit output port. 68 OT1 Output port Note: This output goes high after reset, and internal latch data is output as is even when CLOCK STOP is being executed.
Pins to which power is applied. Normally, VDD = 1.8 to 3.6 V is applied. In back-up mode (when CKSTP instructions are being executed), voltage can be lowered to 1.0 V. If voltage falls below 1.55 V while the CPU is operating, the CPU stops to prevent malfunction (STOP mode). When the voltage rises above 1.55 V, the CPU restarts. STOP mode can be detected by checking the STOP F/F bit. If necessary, execute initialization or adjust clock by program. When detecting or preventing CPU malfunctions using an external circuit, STOP mode can be invalidated and rendered non-operative by program. In that case, all four bits of the internal TEST port should be set to "0". If more than 1.8 V is applied when the pin voltage is 0, the device system is reset and the program starts from address "0". (power on reset) Note: To operate the power on reset, the power supply should start up in 10 to 100 ms. GND VDD
72
VDD
Power-supply pins
69
GND
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Pin No. Symbol Pin Name Function and Operation Using programmable counter input pins for FM, VHF band. The 1/2 + pulse swallow system (VHF mode) and the pulse swallow system (FM mode) are freely selectable by program. 70 FMIN FM local oscillator signal input At the VHF mode, local oscillation output (VCO output) of 50 to 230 MHz [0.3 Vp-p (min)] is input, and at the FM mode, that of 40 to 130 MHz [0.2 Vp-p (min)] is input. A built-in input amp. and C coupling allow operation at low-level input. Note: When in the PLL OFF mode or when set to AMIN input, the input is pulled down. RfIN1 Remarks
Programmable counter input pin for AM band. The pulse swallow system (HF mode) and direct dividing system (LF mode) are freely selectable by program. At the HF mode, local oscillation output (VCO output) of 1 to 45 MHz [0.2 Vp-p (min)] is input, and at the LF mode, 0.9 to 10 MHz [0.2 Vp-p (min)] is input. Built-in input amp. operates with low-level input using a C coupling. Note: When in PLL OFF mode or when set to FMIN input, the input is pulled down. RfIN1
71
AMIN
AM local oscillator signal input
Input pin for system reset signals.
RESET takes place while at low level; at high level, the program starts from address "0".
73
Reset input/Program RESET /VPP voltage supply
Normally, if more than 1.8 V is supplied to VDD when the voltage is 0, the system is reset (power on reset). Accordingly, this pin should be set to high level during operation. This pin is used as program voltage supply for One Time PROM. In case of writing program into the internal PROM, 12.5 V is supplied to this pin.
VPP
74
XOUT
Crystal oscillator pins. A reference 75-kHz crystal resonator is connected to the XIN and XOUT pins. XOUT
ROUT RfXT VXT VIN
75
XIN
Crystal oscillator pin
The oscillator stops oscillating during CKSTP instruction execution. The VXT pin is the power supply for the crystal oscillator. A stabilizing capacitor (0.47 mF typ.) is connected.
76
VXT
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TC93P27F
Pin No. Symbol Pin Name Function and Operation Voltage doubler boosting pin to drive the LCD. 77 VLCD A capacitor (0.1 to 3.3 mF typ.) is connected to boost the voltage. The VLCD pin outputs voltage (3.1 V), which has been doubled from the constant voltage (VEE: 1.55 V) using the capacitor connected between C1 and C2. This potential is supplied to the LCD driver. If the internal VLCD OFF bit is set to "1" by program, an external supply can be input through the VLCD pin to drive the LCD. 79 C2 At this time, the VLCD/2 potential, whose VLCD voltage divided using resisters, is output from the C2 pin. 1.55 V constant voltage supply pin to drive the LCD. 80 VEE Constant voltage supply pin A stabilizing capacitor (0.47 mF typ.) is connected. This is a reference voltage for the A/D converter, key input, and the bias potential of the LCD common output. 3/4 VLCD Remarks
78
C1
Voltage doubler boosting pin
Note 1: When the device is reset (VDD = 0 V (R) 1.8 V or higher or RESET = "L" (R) "H") I/O ports are set to input, the pins for both LCD output and I/O ports and additional functions (e.g., SIO, A/D converter) are set to I/O port input pins, while the IFIN/IN1/SCIN pins become IF input pins. Note 2: When in PLL OFF mode (when the three bits in the internal reference ports are all set to "1"), the IFIN/SCIN and FMIN, AMIN pins are pulled down, and DO1 and DO2 are at high impedance. Note 3: When in CLOCK STOP mode (during execution of CKSTP instruction), the output ports (excluding OT1 output) and LCD output pins are all at low level, while the constant voltage circuit (VEE), the voltage doubler circuit (VLCD), and the power supply for the crystal oscillator (VXT) are at VDD level. Note 4: When the device is being reset, the contents of the output ports and internal ports are undefined and must be initialized via software. Note 5: When the pins for both LCD output and I/O ports are set to the I/O port, VLCD potential is used as the power supply for the output, so the VLCD level is output at "H" level. In addition, the input power supply is at VDD level, so it can be used in the same way as for the other I/O port inputs.
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Maximum Ratings (Ta = 25C)
Characteristics Supply voltage Program voltage Input voltage Power dissipation Operating temperature Storage temperature Symbol VDD VPP VIN PD Topr Tstg Rating -0.3~4.0 -0.3~13.0 -0.3~VDD + 0.3 100 -10~60 -55~125 Unit V V V mW C C
Electrical Characteristics (unless otherwise noted, Ta = 25C, VDD = 3.0 V)
Characteristics Range of operating supply voltage Range of memory retention voltage Symbol VDD VHD Test Circuit 3/4 3/4 Crystal oscillation stopped (CKSTP instruction executed) Under ordinary operation No output load IDD1 3/4 FMIN = 230 MHz input Under ordinary operation No output load Operating current IDD2 3/4 3/4 3/4 3/4 3/4 3/4 Crystal oscillation fXT = 75 kHz FMIN = 130 MHz input Under CPU operation only (PLL off, display turned on) VDD = 3.0 V 3/4 3/4 3/4 3/4 (*) 3/4 3/4 65 130 mA VDD = 3.0 V 3/4 6.0 10 VDD = 3.0 V 3/4 7.0 12 mA Test Condition (*) Min 1.8 1.0 Typ. ~ ~ Max 3.6 3.6 Unit V V
(*)
IDD3
Soft wait mode (crystal oscillator, display circuit operating, CPU stopped, PLL off) Hard wait mode (crystal oscillator operating only) Crystal oscillation stopped (CKSTP instruction executed)
45
90
IDD4 Memory retention current Crystal oscillation frequency Crystal oscillation start-up time IHD fXT tST
35 0.1 75 3/4
70 10 3/4 1.0 mA kHz s
Voltage Doubler Circuit
Characteristics Voltage doubler reference voltage Constant voltage temperature characteristics Voltage doubler boosting voltage Symbol VEE Test Circuit 3/4 3/4 3/4 Test Condition GND reference (VEE) Min 1.35 3/4 Typ. 1.55 -5 Max 1.75 3/4 Unit V
DV
GND reference (VEE)
mV/C
VLCD
GND reference (VLCD)
2.7
3.1
3.5
V
For conditions marked by an asterisk (*), guaranteed when VDD = 1.8 to 3.6 V, Ta = -10 to 60C
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Operating Frequency Ranges for Programmable Counter and LF Counter
Characteristics Symbol Test Circuit 3/4 3/4 3/4 3/4 3/4 Test Condition Sine wave input when VIN = 0.3 Vp-p FMIN (VHF mode) fVHF Sine wave input when VIN = 0.2 Vp-p, VDD = 1.8 to 3.0 V, Ta = -10 to 60C FMIN (FM mode) AMIN (HF mode) AMIN (LF mode) IFIN fFM fHF fLF fIF Sine wave input when VIN = 0.2 Vp-p Sine wave input when VIN = 0.2 Vp-p Sine wave input when VIN = 0.2 Vp-p Sine wave input when VIN = 0.2 Vp-p FMIN input (VHF mode) (*) (*) (*) (*) (*) Input amplitude VIN 3/4 VDD = 1.8 to 3.0 V, Ta = -10 to 60C (*) 40 1 0.9 0.35 0.3 0.2 0.2 ~ ~ ~ ~ ~ ~ ~ 130 45 12 12 VDD - 0.8 VDD - 0.8 VDD - 0.8 Vp-p MHz MHz MHz MHz (*) 50 ~ 230 MHz Min Typ. Max Unit
FMIN (FM mode), AMIN, IFIN input
LCD Common Output/Segment Output, General-Purpose I/O Ports
(COM 1 to COM4, S1 to S16, S17/P7-0 to S25/P9-0, P9-1 to 3, IN2)
Characteristics Output current "H" level "L" level Symbol IOH1 IOL1 VBS ILI VIH1 VIL1 Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 Test Condition VLCD = 3 V, VOH = 2.7 V VLCD = 3 V, VOL = 0.3 V No load VIH = VDD, VIL = 0 V (when using I/O port, IN port) (when using I/O port, IN port) (when using I/O port, IN port) Min -0.4 0.4 1.35 3/4 VDD 0.6 0 Typ. -0.8 0.8 1.55 3/4 ~ ~ Max 3/4 3/4 1.75 1.0 VDD V VDD 0.1 Unit mA
Output voltage 1/2 level Input leak current "H" level Input voltage "L" level
V mA
I/O Port (P1-0 to P1-3)
Characteristics Output current "H" level "L" level Symbol IOH1 IOL1 ILI VIH2 VIL2 RON Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 VOH = 2.7 V VOL = 0.3 V VIH = 3.0 V, VIL = 0 V (when using I/O port) (when using I/O port) (when using I/O port) VOL = 3.0 V (when connected to load resistance) Test Condition Min -0.4 0.4 3/4 2.4 0 50 Typ. -0.8 0.8 3/4 ~ ~ 100 Max 3/4 3/4 1.0 3.0 V 0.6 200 kW Unit mA mA
Input leak current Input voltage "H" level "L" level
N-ch load resistance
For conditions marked by an asterisk (*), guaranteed when VDD = 1.8 to 3.6 V, Ta = -10 to 60C
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HOLD Input Port
Characteristics Input leak current Input voltage "H" level "L" level Symbol ILI VIH3 VIL3 Test Circuit 3/4 3/4 3/4 Test Condition VIH = 3.0 V, VIL = 0 V 3/4 3/4 Min 3/4 2.4 0 Typ. 3/4 ~ ~ Max 1.0 3.0 V 1.2 Unit mA
A/D Converter (ADIN1 to ADIN3, DC-REF)
Characteristics Analog input voltage range Analog reference voltage range Resolution Conversion total error Analog input leak Symbol VAD VREF VRES 3/4 ILI Test Circuit 3/4 3/4 3/4 3/4 3/4 VDD = 2.0 to 3.6 V VIH = 3.0 V, VIL = 0 V (ADIN1 to ADIN3, DC-REF) ADIN1 to ADIN3 DC-REF, VDD = 2.0 to 3.6 V 3/4 Test Condition Min 0 1.0 3/4 3/4 3/4 Typ. ~ ~ 6 1.0 3/4 Max VDD VDD 0.9 3/4 4.0 1.0 Unit V V bit LSB mA
Key Input Port (K0 to K3)
Characteristics Key input voltage range A/D conversion resolution A/D conversion total error N-ch/P-ch input resistance Input voltage "H" level "L" level Symbol VKI VRES 3/4 RIN1 VIH4 VIL4 ILI Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 3/4 VDD = 1.8 to 2.0 V VDD = 2.0 to 3.6 V 3/4 When releasing WAIT instruction When releasing WAIT instruction When input resistance is off, VIH = 3.0 V, VIL = 0 V Test Condition 3/4 3/4 Min 0 3/4 3/4 3/4 50 1.8 0 3/4 Typ. ~ 3 3/4 3/4 100 ~ ~ 3/4 Max VDD 3/4 1.5 0.5 200 3.0 V 0.3 1.0 mA Unit V bit
LSB
kW
Input leak current
DO1/OT2, DO2 Output, Mute, OT1 Output
Characteristics Output current "H" level "L" level Symbol IOH1 IOL1 ITL Test Circuit 3/4 3/4 3/4 VOH = 2.7 V VOL = 0.3 V VTLH = 3.0 V, VTLL = 0 V (DO1, DO2) Test Condition Min -0.4 0.4 3/4 Typ. -0.8 0.8 3/4 Max 3/4 3/4 100 Unit mA nA
Output off leak current
For conditions marked by an asterisk (*), guaranteed when VDD = 1.8 to 3.6 V, Ta = -10 to 60C
13
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TC93P27F
General-Purpose I/O Port (P2-0 to P6-3)
Characteristics Output current "H" level "L" level Symbol IOH1 IOL1 ILI VIH2 VIL2 Test Circuit 3/4 3/4 3/4 3/4 3/4 VOH = 2.7 V VOL = 0.3 V VIH = 3.0 V, VIL = 0 V 3/4 3/4 Test Condition Min -0.4 0.4 3/4 2.4 0 Typ. -0.8 0.8 3/4 ~ ~ Max 3/4 3/4 1.0 3.0 V 0.6 Unit mA mA
Input leak current Input voltage "H" level "L" level
IN1/SCIN, RESET Input Port
Characteristics Input leak current Input voltage "H" level "L" level Symbol ILI VIH2 VIL2 Test Circuit 3/4 3/4 3/4 Test Condition VIH = 3.0 V, VIL = 0 V (excluding SCIN input) 3/4 3/4 Min 3/4 2.4 0 Typ. 3/4 ~ ~ Max 1.0 3.0 V 0.6 Unit mA
Others
Characteristics Input pull-down resistance XIN amp. feedback resistance XOUT output resistance Input amp. feedback resistance Voltage drop detection voltage Voltage drop detection temperature property Symbol RIN2 RfXT ROUT RfIN1 RfIN2 VSTP Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 3/4 (TEST) (XIN-XOUT) (XOUT) (FMIN, AMIN) (IFIN/SCIN) (VDD) Test Condition Min 15 3/4 3/4 150 500 1.35 3/4 Typ. 30 20 4 300 1000 1.55 -3 Max 60 3/4 3/4 600 kW 2000 1.75 3/4 V Unit kW MW kW
DS
(VDD)
mV/C
For conditions marked by an asterisk (*), guaranteed when VDD = 1.8 to 3.6 V, Ta = -10 to 60C
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TC93P27F
Package Dimensions
Weight: 0.45 g (typ.)
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TC93P27F
RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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